The preferred embodiments relate to integrated circuit manufacture and devices and, more particularly, to three dimensional integrated circuit capacitors.
Integrated circuits typically include numerous devices and interconnections, formed relative to a semiconductor substrate. These devices may include transistors, capacitors, resistors, and others. As technology advances, these devices become smaller, yet considerations such as performance, reliability, and cost remain vitally important. The preferred embodiments relate primarily to capacitors, and for such devices therefore a desirable goal is to achieve sufficient and sometimes relatively large capacitance within a particular area or volume, with another goal being the use of such a capacitance in higher voltage applications.
Integrated circuit capacitors in connection with the above considerations have included what are sometimes categorized as either two or three dimensional architectures. A typical two-dimensional integrated circuit capacitor is formed by including an insulating layer, having a dielectric constant, between two planar conductors. For example, such a capacitor may be formed by locating an insulating layer between a first conductor, such as be a doped semiconductor region, polysilicon layer, or a semiconductor substrate, and a second conductor, such as a layer of doped polysilicon. A three dimensional integrated circuit capacitor is so named because the path from one conductor to the other, through the intermediate insulating dielectric, extends in more than one direction. Certain examples may be found in U.S. Pat. No. 6,902,939, entitled “Integrated Circuit and Method,” issued Jun. 7, 2005, such as in its FIGS. 13a through 13i. 
Given the preceding, the present inventors seek to improve upon the prior art, as further detailed below.